1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits including vertical nanowires.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, which include, in particular, field effect transistors. In a field effect transistor, a gate electrode is provided that can be separated form a channel region by a gate insulation layer providing electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are provided.
The channel region, the source region and the drain region can be formed of a semiconductor material, wherein the doping of the channel region is different from the doping of the source region and the drain region. Depending on an electric voltage applied to the gate electrode, the field effect transistor can be switched between an on-state and an off-state.
Field effect transistors can be planar field effect transistors, wherein the source region, the channel region and the drain region are formed in a semiconductor substrate or in a layer of a semiconductor material provided above a substrate. The source region, the channel region and the drain region are arranged along a horizontal direction of the substrate that is substantially perpendicular to a vertical direction being a thickness direction of the substrate. Above the channel region, a gate electrode is formed, and a gate insulation layer may be provided between the gate electrode and the channel region for electrically insulating the gate electrode from the channel region.
For increasing the speed of operation of field effect transistors and for providing a higher density of integration of integrated circuits including field effect transistors, a reduction of the size of the field effect transistors may be required. If the size of a planar field effect transistor is reduced, a gate length corresponding to a distance between the source region and the drain region of the transistor is also reduced. This can lead to short channel effects, which include an increased leakage current and a worse sub-threshold slope of the field effect transistor.
For addressing some performance issues that can occur if planar field effect transistors are employed in an integrated circuit, it has been proposed to use FinFET or tri-gate transistors, respectively, instead of planar field effect transistors. In FinFET and tri-gate transistors, the channel region and/or the source and drain regions, or portions of the source and drain regions, are formed in fins, which are elongated semiconductor elements extending along a horizontal direction of a substrate on which the transistors are formed. The gate electrode can be formed on two sides of the fins and, in the case of tri-gate transistors, also on top of the fins, so that the gate electrode is provided on three sides of the fins.
Thus, an electric voltage applied to the gate electrode of a FinFET or tri-gate transistor is provided on two or three sides of the channel region, respectively, which can improve the controllability of the channel region. However, similar to planar transistors, in FinFET and tri-gate transistors, the source, channel and drain regions are arranged along a horizontal direction of the substrate, requiring a relatively large amount of space for providing electrical contacts to the source and drain regions and for the gate length.
In view of the situation described above, methods that overcome or at least reduce some or all of the above-mentioned issues are provided. In particular, the present disclosure provides methods that may be employed for forming field effect transistors wherein the source, channel and drain region are arranged along a vertical direction of a substrate on which the transistors are formed. This may allow a reduction of the extension of the field effect transistors in horizontal directions of the substrate, without requiring a scaling of the gate length of the transistors. Furthermore, the present disclosure provides methods that may allow the formation of field effect transistors having an improved controllability of the channel.